Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. Chip speeds continue to increase and the amount of data communicated between chips continues to increase to meet the demands of system applications. As the volume of digital data communicated between chips increases, higher bandwidth communication links are needed to prevent data communication bottlenecks between chips. Higher bandwidth communication links can be made by communicating more signals in parallel and/or increasing input/output (I/O) bit speeds.
Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), and pseudo static RAM (PSRAM). Some computer systems include mobile system applications, which have limited space and limited power resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and power consumption are issues for future generations. To address these issues, the industry is developing DRAM for mobile applications.
A DRAM, typically, includes one transistor and one capacitor memory cells arranged in one or more arrays of memory cells, which are arranged in memory banks. To read and write memory cells, each DRAM includes one or more row decoders, one or more column decoders, primary sense amplifiers, and secondary sense amplifiers. The primary sense amplifiers can be differential sense amplifiers, wherein each sense amplifier receives one bit line at each of two differential inputs.
To read or write memory cells, the DRAM receives a row address, a column address, and control signals, such as row address select (RAS) and column address select (CAS) signals. A row decoder receives the row address to select a row of memory cells and the row address is latched into the row decoder via the RAS signal. A column decoder receives the column address to select one or more columns of memory cells and the column address is latched into the column decoder via the CAS signal. Each memory cell at the intersection of a selected row and a selected column provides a data bit to a primary sense amplifier.
At each primary sense amplifier that receives data, one of the bit lines receives the data bit from a selected memory cell and the other bit line is used as a reference. To write a data bit into a selected memory cell, input drivers overdrive the primary sense amplifier. One input driver overdrives a data bit value onto the bit line that is connected to the selected memory cell and another input driver overdrives the inverse of the data bit value onto the reference bit line. To read the data bit, the primary sense amplifier amplifies the difference between the data bit value and the reference value and provides the data bit value to a secondary sense amplifier. The secondary sense amplifier receives the data bit value and provides a data bit output signal.
The secondary sense amplifiers are activated or turned on during each read command. Often, multiple data bits are read via a single read command and multiple secondary sense amplifiers, such as 64 or 128 secondary sense amplifiers, are turned on in parallel. The activated secondary sense amplifiers draw a large current through the power supply lines that may cause a drop in the power supply voltage at points distant from the power supply source. Drops in power supply voltage may cause the DRAM to become unreliable. Also, increasing bandwidth by communicating more signals in parallel and/or by increasing current consumption to make the secondary sense amplifiers faster exacerbates these reliability and power consumption problems.
For these and other reasons there is a need for the present invention.